Switching Behaviour of MOSFET
MOSFET Switching Behavior
To understand MOSFET especially for high power application, we need to understand the switching behaviour of a MOSFET. We will explore the following with simulation and calculations.
1. How the MOSFET switch ON and OFF?
2. Determine the switching time when ON and OFF
3. Determine the power loss
4. Demonstrate with an example to determine the values above by simulation and computation.
MOSFET reference model
Reference: https://www.vishay.com/docs/73217/an608a.pdf
Mosfet Model
Turn On characteristics
VGS - Actual Gate Voltage (From Driver)
VDS - Actual Drain-Source Voltage
Description for turn on at t1,t2,t3
t1 = charging the gate capacitance, gate voltage rises from zero to VTH (threshold voltage)
t1 = charging the gate capacitance, gate voltage rises from zero to VTH (threshold voltage)
At t1, Ids starts increasing since the channel is opened
t2 = charging the gate capacitance, gate voltage rise from zero to Vgp (gate plateau voltage)
At t2, Ids peaks when the voltage reach the plateau voltage between (from t1 to t2)
Between t1 to t2 is the Ids transition from zero to max
t3 = after Vgs reach Vpg and dwell pass t2, channel is fully opened, Vds start to fall. Note that during t3, Vgs dwells in Vgp and gate current charges the gate-drain capacitance Cgd.
At t3, Vds starts to fall, at the end of t3, the drain voltage is near zero. Current flow in gate can be computed with Ig = Cgd(dy/dt) = (Vgs-Vgp)/Rg
dt = CgdRg*(VDS/(Vgs-Vgp) = t3, where dv = VDS-0
Ciss for t1 and t2 refers to the Ciss when VDS = Vds (actual VDS)
Cgd is difficult to determine because VDS is changing
However, it mentioned that using equation t3 to estimate the t3 is difficult because Cgd varies with VDS. When VDS increases, Cgd reduces. To use the data from the datasheet, we can use the modify the equation
where QGD(D) is the charge between G and D at VDS(D) provided by the datasheet
For minimal switching loss, (t2-t1) and t3 must be reduced.
Turn Off characteristics
Description of Turn off at t4,t5,t6
t4 starts when VGS at the driver = 0v
t4 = discharging the gate capacitance, gate voltage fall to Vgp (gate plateau voltage) from VGS. t4 is the time for the gate voltage to fall to Vgp, which constitute to the delay before gate starts restricting.
t5 = gate voltage falling below Vgp cause the channel closing, the drain voltage starts rising, causing the gate current to flow from drain to gate capacitor Cgd preventing the gate voltage from falling, thus maintaining the gate voltage at Vgp (gate plateau voltage) during this period
Ig= Cgd(dv/dt) = (Vgp - 0)/Rg
dt = Cgd*Rg*VDS/Vgp, where dt = t5 and dv = VDS
t6 = discharging the gate capacitance, gate voltage falls to VTH
After t5, the current from the drain is insufficient to maintain Vgp and start falling below Vgp, then the drain current starts falling till Vgs reach Vth at t6, when the channel is closed totally and Ids = 0
Note Ciss at t4 is not the same Ciss at t6, because at t4, VDS = 0V but at t6, VDS = vds
Cgd is difficult to determine because VDS is changing
However, it mentioned that using equation t3 to estimate the t3 is difficult because Cgd varies with VDS. When VDS increases, Cgd reduces. To use the data from the datasheet, we can use the modify the equation where QGD(D) is the QGD charge state at VDS(D) in the datasheet.
For minimal switching loss, t5 and t6 must be reduced
From the equation it is clear that to get the shorted transition time for (t2-t1) and t3 for turn on and t5 and t6 for turn off, the proper MOSFET must to selected with the lowest Ciss and lowest Rg. It also depends on the driver that it able to provide sufficient Source/Sink to drive Vgs behavour to meet t3 and t5 requirement.
How much source and sink current is needed for drivers?
Observe that the gate current peaks during the Vds voltage transit sourcing when turning ON and sinking when turning OFF and the peak current is determined by
Ig (peak source) = (VGS-Vgp)/Rg (refer to t3)
Ig (peak sink) = (0 - Vgp)/Rg (refer to t5)
If Vgp < VGS < 2Vgp, then Ig(peak sink) > Ig (peak source)
If VGS > 2Vgp, then Ig(peak source) > Ig (peak sink)
How to estimate switching time of a selected MOSFET with the following charges?
We need to use the total gate-source charge to estimate the switching time.
QG = QGS+QGD+QOD
Note that the above computation is true only if the driver provides sufficient current to charge QGS and QGD.
Response Time Definition
Definition of the delay and rise/fall time are given below
td(on) - Time on delay between gate to drain
td(off) - Time off delay between gate to drain
td(off) - Time off delay between gate to drain
tr - Drain turn on fall time
tf - Drain turn off rise time
Driver current
To determine the required driver current, it cannot be determined directly using the input capacitance Ciss, which is input capacitance with the drain shorted, meaning Ciss = Cgs+Cgd, because the capacitance to the gate affecting the delay starts before the drain is turned on (when turn on) and continues to delay the turn off (when turning off) after the drain is off. The means the equivalent capacitance affecting the delay in turn on and turn off is higher than Ciss.
A more accurate way to estimate the turn off and turn on is using the total gate charge QG which is also stated in the datasheet
The total gate charge, QG, that must be dispensed into the equivalent gate capacitance of the MOSFET to achieve turn-on is given as: QG = QGS + QGD + QOD
where:
QG is the total gate charge
QGS is the gate-to-source charge
QGD is the gate-to-drain Miller charge
QOD is the “overdrive charge” after charging the Miller capacitance.
In equation form:
QG = (CEI)(VGS) and
IG = QG/t(transition)
where:
QG is the total gate charge, as defined above
CEI is the equivalent gate capacitance
VGS is the gate-to-source voltage
IG is the gate current required to turn the MOSFET on in time period t(transition)
t(transition) is the desired transition time
MOSFET IRF840
Example IRF840, QG = 40nC (Vds@100V, Vgs = 10V)
Desired switching time = 50nS
IG(peak) = 40/50 = 0.8A
What happens when the max gate current is 0.25A
t(transition) = 40/0.25 = 160nS
Gate Resistor (Rg)
To protect the gate driver, a gate resistor can be connected to limit the current
Rg(ext) = Vdr-Vg(th)/IG(peak)
For example gate voltage peak = 12V, with IG=0.25A
Worst case Vg(TH) = 4V
Rg(ext) = (12-4)/0.25 = 32 ohms
This means the largest series resistor to limit the current for the gate is 32 ohms
Note that this resistor also reduces ringing due to trace inductance.
Simulated Gate Drivers
Once the required gate current is determined, lets look at the design for simulated gate driver that has both sink and source capability.
With R2 = 1K ohm
A simulated driver can be represented by a Source/Sink with resistor R2 as the external gate resistor.
Simulated Results
Output T(on) Delay = 3.8us (by observing when Vgp start rising from plateau)
T(fall) = 1.8us
Output T(off) Delay = 8.6us (by observing when Vgp start falling from plateau)
T(rise) = 3us
R2 has limited the peak gate current to 10mA (sink or source), controlling the response time for both transitions. Notice when the Vgs is at the plateau voltage level, the source current Ig = -(VGS-Vgp)/1k = -6mA and sink current Ig = Vgp/Rg = 4mA
Let's verify by computation
Before turn on, Vgs =0V, Vds = 100V
Ciss = 1300P, Rg = 1K + 2.8, Vds = 100, Vgs = 0 to 10V
Transition time (Drain switching H to L), t3 = Rg*(QGD(D)/VDS(D)) *Vds/[Vgs-Vgp]
Let say Vt = 4 (datasheet 2~4V)
Vgp ~= Vth+I/Gfs = Vgs+(Vg-Vt)/(Rg*Gfs) = 4+(10-4)/(1002.8*4.9) = 4.001
Cgd (Crss) = 120pf (VDS@25V, Vgs=0)
Qgd (@400V) = 32nC
Cgd = 32/400 = 80pf (VDS@400V, Vgs=10)
Note from the table above, Crss (Cgd) is almost flat after VDS>40V
t1 = 1300*1002.8 * ln (10/(10-4)) = 0.664us
t2 = 1300*1002.8 * ln (10/(10-4.001)) = 0.666us
t3 = 1002.8 *(32/400)* 100/[10-4.001]) = 1.337us
T(on) delay = t2= 0.67 us
T(fall) ~= t3 = 1.337 us
Note Ciss in this case is not the same as Ciss when switching on, because VDS=0V which has a larger Ciss
Ciss = 2300pf (@VDS=0)
Ciss = 1300pf (@VDS = 100V)
Transition time (Drain switching L to H), t6 = Rg*(QGD(D)/VDS(D)) *Vds/[Vgp]
t4 = 2300*1002.8* ln (10/4.001) = 2.12us (Use Ciss when VDS = 0)
t5 = 1002.8*(32/400)*(100/4.001) = 2.005us (Use QGD to estimate CGD)
t6 = 1300*1002.8* ln (4.001/4) = 0.33us (Use Ciss when VDS = 100)
T(off) = t4 = 2.12us
T(rise) ~= t5 = 2.005us
With R2 = 10 ohms
If R2 is reduced to 10 ohm, the delay is shortened, but the switching current has risen to 750mA
Observations
1. Gate current for source and sink has peaked at more than 600mA.
2. The gate voltage at the plateau period for turn on and turn off are not at the same level. The reason for this is not that the plateau voltage has changed. The gate voltage must include the voltage drop in the gate internal resistance. Taking Vgp~=Vt = 4V and Ipeak at 0.7A
Vgs = Vgp + Ig*Rg(internal)
Vgs (source) = 4 + 0.7*2.8 = 5.96V
Vgs (sink) = 4 -0.7*2.8 = 2.04V
From the simulation, you can see that when the MOSFET is on, Vgs = 6V and it is off, Vgs = 2.2V
3. Notice that the switch off is taking longer than switching on. The Vgp is falling lower switching off than switching on. It is taking longer to discharge the gate charges in the switch off period. This is likely caused by the drain-source inductance slowing the drain current collapse and the reverse recovery of the body diode taking time to clear its charge when switching off.
T(on) Delay = 13ns (On delay)
tf = 21ns (fall time for VDS)
T(off) Delay = 130ns (Off delay)
tr = 31ns (rise time for VDS)
Vgp ~= Vt + Ig/Gfs
Ig = (Vg-Vt)/(Rg)
Vgp = 4 + (10-4)/(12.8*4.9) = 4.1
Qgd (VDS@400V) = 32nC
Ciss (VDS@ 100V) = 1300pf
t1 = 1300*12.8 * ln (10/(10-4)) = 8.5ns (Use Ciss when VDS = 100)
t2 = 1300*12.8 * ln (10/(10-4.1)) = 8.8ns (Use Ciss when VDS = 100)
t3 = 12.8 * 32/400*100/[10-4.1]) = 17.4ns
T(on) delay = t2 = 8.8ns
T(fall) switch = t3 = 17.4ns
Switching On time (Vds or Ids change) = t3+(t2-t1) = 17.4+0.3 =17.7
Qgd (VDS@400V) = 32nC
Ciss (VDS@ 100V) = 1300pf
Ciss (VDS@ 0V) = 2300pf
t4 = 2300*12.8 *ln (10/4.1) = 26.2ns (Use Ciss when VDS = 0)
t5 = 12.8 *32/400* (100/4.1) = 24.4ns
t6 = 1300*12.8* ln(4.1/4) = 0.41ns (Use Ciss when VDS = 100)
T(off) delay = t4 = 26.2ns
T(rise) switch ~= t5 = 24.4ns
Switching Off time (Vds or Ids change) = t5+t6 = 24.4+0.41 = 24.81
Observe that the calculated fall and rise time are quite close to the simulated values, the delay for T(off) is significantly larger in simulation. This difference is likely caused by the delay cause by the parasitic inductance between the drain and gate that slows and turn-off drain current thus extending the Vgp period at the gate.
Notice also that the switching loss mainly occur during the change of Vds and Ids. So for switching time for turn on (t3+(t2-t1)) and turn off (t5+t6)
Power Loss
Power Loss of the mosfet determines how much heat is built up at the mosfet. The greater the heat, the higher the temperature of the mosfet. The objective is to try to design a driver that cause a minimal heat loss and thus reducing the normal operating temperature of the mosfet
Using the simple driver above, what is the simulated power loss at 50khz with duty cycle 50%?
Using SIMETRIX "measure" function the mean power/cycle is determined.
With Rg = 10 ohms
Power Loss = 466mW
With Rg = 1k
Power Loss = 3.75W
Observe that gate current (determined by Rg) has a significant effect on power loss.
How to determines MOSFET power loss by calculation?
Using Rg = 10ohms, the following are computed,
1. Conduction Loss
Irms = V/RL*D where
V = drain supply voltage
RL = Drain Load
RDS(on) = 0.85 ohm
D = On Duty Cycle
Irms = 100/100*0.5 = 0.5A (Duty 50%)
Pcond = 0.5*0.5*0.85 = 0.2125W
2. Switching Loss
Using the computed values found earlier,
tF and tR is the transit time where Vds or Ids switches
ton ~= t3+(t2-t1) = 17.7ns
toff ~= t5+t6 = 24.81ns
Psw = 0.5 * 100 * (100/100) *((17.7 + 24.81)/1000000000) * 500000
Psw = 0.5 * 100 * 1 *(42.51)/1000000000) * 500000 = 0.106W
3 Gate Loss
Pgate = 40/1000000000*10*500000 = 0.02W
4. Output Capacitance Loss
Pcoss = 0.5*(125/1000000000000)*100*100*50000 = 0.03W
Total power loss = Pcond + Psw + Pgate = 0.2125+0.106+0.02 + 0.03 = 0.3685W
Observe the following
1. Switching Loss is relatively lower than the conduction loss in this case.
2. Gate Loss and Output capacitance Loss are relatively smaller than conduction and switching losses
3. The computed result is very close to the simulated result of 0.460W.
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